AD9023 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. functional block diagram 4-bit adc dac dac 5-bit adc digital error correction 5-bit adc 12 8 ecl t/h +2v ref gnd +5v ?.2v encode analog input encode t/h 16 with dnl typically less than 0.5 lsb and 20 ns transient re- sponse settling time, the AD9023 provides excellent results when low frequency analog inputs must be over-sampled (such as ccd digitization). the full-scale analog input is 1 v with a 300 w input impedance. the analog input can be driven directly from the signal source, or can be buffered by the ad96xx series of low noise, low distortion buffer amplifiers. all timing is internal to the AD9023; the clock signal initiates the conversion cycle. for best results, the encode command should contain as little jitter as possible. high speed layout prac- tices must be followed to ensure optimum a/d performance. the AD9023 is built on a trench isolated bipolar process and utilizes an innovative multipass architecture (see the block dia- gram). the unit is packaged in 28-pin ceramic dips and gullwing surface mount packages. the AD9023 is specified to operate over the industrial (C25 c to +85 c) and extended (C55 c to +125 c) temperature ranges. 12-bit 20 msps monolithic a/d converter features monolithic 12-bit 20 msps a/d converter low power dissipation: 1.5 watts on-chip t/h and reference high spurious-free dynamic range ecl logic applications radar receivers digital communications digital instrumentation electro-optic medical imaging digital filters product description the AD9023 is a high speed, high performance, monolithic 12- bit analog-to-digital converter. all necessary functions, includ- ing track-and-hold (t/h) and reference, are included on chip to provide a complete conversion solution. it is a companion unit to the ad9022; the primary difference between the two is that all logic for the ad9022 is ttl compatible, while the AD9023 utilizes ecl logic for digital inputs and outputs. pinouts for the two parts are nearly identical. operating from +5 v and C5.2 v supplies, the AD9023 provides excellent dynamic performance. sampling at 20 msps with a in = 1 mhz, the spurious-free dynamic range (sfdr) is typi- cally 74 db; with a in = 9.6 mhz, sfdr is 72 db. snr is typi- cally 65 db. the on-board t/h has a 110 mhz bandwidth and, more impor- tantly, is designed to provide excellent dynamic performance for analog input frequencies above nyquist. this feature is neces- sary in many undersampling signal processing applications, such as in direct if-to-digital conversion. to maintain dynamic performance at higher ifs, monolithic rf track-and-holds (such as the ad9100 and ad9101 samplifier?) can be used with the AD9023 to process signals up to and beyond 70 mhz. samplifier is a trademark of analog devices, inc. rev. a
rev. a C2C AD9023Cspecifications electrical characteristics test AD9023aq/az AD9023bq/bz AD9023sq/sz parameter (conditions) temp level min typ max min typ max min typ max units resolution 12 12 12 bits dc accuracy differential nonlinearity +25 c i 0.6 0.75 0.4 0.5 0.6 0.75 lsb full vi 1.0 1.0 1.0 lsb integral nonlinearity +25 c i 1.2 2.5 1.2 2.0 1.2 2.5 lsb full vi 1.6 3.0 1.6 3.0 1.6 3.0 lsb no missing codes full vi guaranteed guaranteed guaranteed offset error +25 ci 525 525 525 mv full vi 15 35 15 35 15 35 mv gain error +25 c i 0.5 2.5 0.5 2.5 0.5 2.5 % fs full vi 0.6 3.5 0.6 3.5 0.6 3.5 % fs thermal noise +25 c v 0.57 0.57 0.57 lsb, rms analog input input voltage range 1.024 1.024 1.024 v input resistance full iv 240 300 360 240 300 360 240 300 360 w input capacitance +25 cv 6 6 6 pf analog bandwidth +25 c v 110 110 110 mhz switching performance 1 minimum conversion rate +25 c iv 4 4 4 msps maximum conversion rate full vi 20 20 20 msps aperture delay (t a ) +25 c iv 0.50 0.78 1.05 0.50 0.78 1.05 0.50 0.78 1.05 ns aperture uncertainty (jitter) +25 c v 5 5 5 ps, rms output delay (t od ) full vi 8.5 19.5 8.5 19.5 8.5 19.5 ns encode input logic compatibility ecl ecl ecl logic 1 voltage full vi C1.1 C1.1 C1.1 v logic 0 voltage full vi C1.5 C1.5 C1.5 v logic 1 current full vi 5 20 5 20 5 20 m a logic 0 current full vi 5 20 5 20 5 20 m a input capacitance +25 cv 6 6 6 pf pulse width (high) +25 c iv 22.5 125 22.5 125 22.5 125 ns pulse width (low) +25 c iv 20 125 20 125 20 125 ns dynamic performance transient response +25 c v 20 20 20 ns overvoltage recovery time +25 c v 20 20 20 ns harmonic distortion 2 analog input @ 1.2 mhz +25 c i 65 72 70 74 65 72 dbc @ 1.2 mhz full 72 74 72 dbc @ 4.3 mhz +25 c v 72 74 72 dbc @ 9.6 mhz +25 c i 63 69 69 71 63 69 dbc @ 9.6 mhz full 68 71 68 dbc signal-to-noise ratio 2 analog input @ 1.2 mhz +25 c i 62 63 64 65 62 63 db @ 1.2 mhz full v 62 64 62 db @ 4.3 mhz +25 c v 63 65 63 db @ 9.6 mhz +25 c i 61 62 63 64 61 62 db @ 9.6 mhz full v 62 64 62 db signal-to-noise ratio 2 (without harmonics) analog input @ 1.2 mhz +25 c i 63 64 65 66 63 64 db @ 1.2 mhz full v 63 65 63 db @ 4.3 mhz +25 c v 64 66 64 db @ 9.6 mhz +25 c i 62 63 64 65 62 63 db @ 9.6 mhz full v 62 64 62 db (+v s = +5 v; Cv s = C5.2 v; encode = 20 msps, unless otherwise noted)
AD9023 rev. a C3C test AD9023aq/az AD9023bq/bz AD9023sq/sz parameter (conditions) temp level min typ max min typ max min typ max units two-tone intermodulation +25 c v 74 74 74 dbc distortion rejection 3 digital outputs 1 logic compatibility ecl ecl ecl logic 1 voltage full vi C1.1 C1.1 C1.1 v logic 0 voltage full vi C1.5 C1.5 C1.5 v output coding offset binary offset binary offset binary power supply +v s supply voltage full vi 4.75 5.0 5.25 4.75 5.0 5.25 4.75 5.0 5.25 ma +v s supply current full vi 100 120 100 120 100 120 ma Cv s supply voltage full vi C5.45 C5.2 C4.95 C5.45 C5.2 C4.95 C5.45 C5.2 C4.95 ma Cv s supply current full vi 195 240 195 240 195 240 ma power dissipation full vi 1.5 2.0 1.5 2.0 1.5 2.0 w power supply rejection ratio (psrr) 4 full v 32 32 32 mv/v notes 1 AD9023 load is 100 w to C2.0 v. 2 rms signal-to-rms noise with analog input signal 1 db below full scale at specified frequency. 3 intermodulation measured with analog input frequencies of 8.9 mhz and 9.8 mhz at 7 db below full scale. 4 psrr is sensitivity of offset error to power supply variations within the 5% limits shown. specifications subject to change without notice. absolute maximum ratings 1 +v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v Cv s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C6 v analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s to +v s digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s to 0 v digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature range AD9023aq/az/bq/bz . . . . . . . . . . . . . . . C25 c to +85 c AD9023sq/sz . . . . . . . . . . . . . . . . . . . . . C55 c to +125 c maximum junction temperature 2 . . . . . . . . . . . . . . . . . . . . . . . . +175 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . +300 c storage temperature range . . . . . . . . . . . . C65 c to +150 c notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances: q package (ceramic dip): q jc = 10 c/w; q ja = 35 c/w. z package (gullwing surface mount): q jc = 13 c/w; q ja = 45 c/w. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9023 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recom- mended to avoid performance degradation or loss of functionality. warning! esd sensitive device
C4C AD9023 rev. a die layout and mechanical information die dimensions . . . . . . . . . . . . . . . . 205 228 21 ( 1) mils pad dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 mils metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . none substrate potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cv s transistor count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4,128 passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . oxynitride bond wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . aluminum compensation gnd ? s +v s analog input ? s +v s ? s gnd d3 d2 d1 d11 (msb) d10 d9 d8 d7 d6 d5 d4 gnd +v s gnd encode gnd d0 (lsb) encode ordering guide temperature package package model range description option AD9023aq/bq C25 c to +85 c 28-pin ceramic dip q-28 AD9023az/bz C25 c to +85 c 28-pin ceramic z-28 leaded chip carrier AD9023sq C55 c to +125 c 28-pin ceramic dip q-28 AD9023sz C55 c to +125 c 28-pin ceramic z-28 leaded chip carrier explanation of test levels test level i C 100% production tested. ii C 100% production tested at +25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C all devices are 100% production tested at +25 c; guaranteed by design and characterization testing at temperature extremes for industrial devices. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9023 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recom- mended to avoid performance degradation or loss of functionality. warning! esd sensitive device n ?2 n ?1 data output n n ?3 n n + 1 analog in t od = 8.5?9.5ns typical t a = 0.8 typical n + 2 t a t od encode encode timing diagram
AD9023 rev. a C5C pin description pin no. name function 1C3 d3Cd1 digital output bits of adc; ecl compatible. 4 d0 (lsb) least significant bit of adc output; ecl compatible. 5 encode complementary encode input to adc. 6 nc no connect 7 gnd ground 8 encode encode clock input to adc. internal t/h is placed in hold mode (adc is encoding) on rising edge of encode signal. 9 gnd ground 10 +v s +5 v power supply 11 gnd ground 12 a in noninverting input to t/h amplifier. 13 Cv s C5.2 v power supply 14 +v s +5 v power supply 15 Cv s C5.2 v power supply 16 gnd ground 17 comp should be connected to Cv s through 0.1 m f capacitor. 18 d11 (msb) most significant bit of adc output; ecl compatible. 19C25 d10Cd4 digital output bits of adc; ecl compatible. 26 +v s +5 v power supply 27 Cv s C5.2 v power supply 28 gnd ground pin designations +v s analog input ? s +v s 180 120 10 pf 20pf 50 compensation ? s ? s 3400 3400 encode ? s encode 1200 d0 ?d11 ? s figure 1. equivalent circuits compensation analog input encode input output stage nc = no connect compensation (pin 17) should be connected to ? s through 0.1 m f d3 d2 gnd ? s nc gnd d5 d6 d7 d1 d0 (lsb) +v s d4 encode d8 gnd d9 +v s d10 gnd d11 (msb) a in comp ? s gnd +v s ? s 13 18 1 2 28 27 5 6 7 24 23 22 3 4 26 25 8 21 9 20 10 19 11 12 17 16 14 15 top view (not to scale) AD9023 encode
C6C AD9023 rev. a typical characteristics ?3 10 1 0 ?2 9 8 7 6 5 4 3 2 ?1 ?0 ?9 ?8 ?7 ?6 ?5 worst case harmonic distortion ?dbc analog input frequency ?mhz +125 c ?5 c +25 c figure 2. harmonic distortion vs. analog input frequency 70 1.24 65 60 55 50 45 40 35 4.3 6.3 8.3 10.3 12.3 14.3 16.3 18.3 20.3 analog input frequency ?mhz snr ?db +25 c ?5 c +125 c figure 5. signal-to-noise ratio vs. analog input frequency 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 2.0 4.0 6.0 8.0 frequency ?mhz full scale ?db a in = 1.2mhz a in = ?.0dbfs snr = 66.12db thd = 73.96db sfdr = 76.99dbfs figure 8. fft plot 85 7.5 5 12.5 10 80 75 70 65 60 55 15 17.5 20 22.5 25 encode rate ?msps harmonics and snr ?db snr worst harmonics a in = 1.2mhz figure 3. snr and harmonics vs. en- code rate 90 80 70 60 50 40 30 20 10 0 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? ? a in = 1.2mhz encode = 20mhz sfdr snr input level ?db sfdr and snr ?db figure 6. sfdr and snr vs. input level 0.0 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 frequency ?mhz full scale ?db a in = 9.6mhz a in = ?.0dbfs snr = 65.89db thd = 70.16db sfdr = 70.94dbfs figure 9. fft plot +2.0 0 +1.0 1024 +1.5 +0.5 ?.5 ?.0 ?.5 ?.0 2048 3072 4096 output code differential nonlinearity ?lsbs a in = 1.2mhz f s = 20msps figure 4. differential nonlinearity vs. output code 80 0 20 10 ?0 40 30 50 60 70 input level ?db sfdr and snr ?db a in = 9.6mhz encode = 20mhz ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? ? sfdr snr figure 7. sfdr and snr vs. analog input level 0 20 40 60 80 120 100 0.0 2.0 4.0 6.0 8.0 10.0 frequency ?mhz full scale ?db a in 1 = 8.9mhz a in 2 = 9.8mhz a in 1 = ?.0dbfs a in 2 = ?.0dbfs sfdr = 81.10dbfs figure 10. two tone fft
AD9023 rev. a C7C theory of operation refer to the block diagram. the AD9023 employs a three pass subranging architecture and digital error correction. this com- bination of design techniques insures 12-bit accuracy at rela- tively low power. analog input signals are immediately attenuated through a resis- tor divider and applied directly to the sampling bridge of the track-and-hold (t/h). the t/h holds whatever analog value is present when the unit is strobed with an encode command. the conversion process begins on the rising edge of this pulse, which should conform to the minimum and maximum pulse width requirements shown in the specifications. operation be- low the recommended encode rate (4 msps) may result in ex- cessive droop in the internal t/h devicesCleading to large dc and ac errors. the held analog value of the first track-and-hold is applied to a 5-bit flash converter and a second t/h. the 5-bit flash con- verter resolves the most significant bits (msbs) of the held ana- log voltage. these 5 bits are reconstructed via a 5-bit dac and subtracted from the original t/h output signal to form a residue signal. a second t/h holds the amplified residue signal while it is en- coded with a second 5-bit flash adc. again the 5 bits are re- constructed and subtracted from the second t/h output to form a residue signal. this residue is amplified and encoded with a 4- bit flash adc to provide the 3 least significant bits (lsbs) of the digital output and one bit of error correction. digital error correction logic aligns the data from the three flash converters and presents the result as a 12-bit parallel digi- tal word. the output stage of the AD9023 is ecl. output data may be strobed on the rising edge of the encode command. AD9023 noise performance high speed, wide bandwidth adcs such as the AD9023 are op- timized for dynamic performance over a wide range of analog input frequencies. however, there are many applications (imag- ing, instrumentation, etc.) where dc precision is also important. due to the wide input bandwidth of the AD9023 for a given in- put voltage, there will be a range of output codes which may oc- cur. this is caused by unavoidable circuit noise within the wideband circuits in the adc. if a dc signal is applied to the adc and several thousand outputs are recorded, a distribution of codes such as that shown in the histogram below may result. relative frequency of occurrence x? x? x+3 x+2 x+1 x x? output code one standard deviation = rms noise level figure 11. equivalent input noise the correct code appears most of the time, but adjacent codes also appear with reduced probability. if a normal probability density curve is fitted to this gaussian distribution of codes, the standard deviation will be equal to the equivalent input rms noise of the adc. the rms noise may also be approximated by converting the snr, as measured by a low frequency fft, to an equivalent input noise. this method is accurate only if the snr performance is dominated by random thermal noise (the low frequency snr without harmonics is the best measure). sixty-three db equates to 1 lsb rms for a 2 v p-p (0.707 v rms) input signal. the AD9023 has approximately 0.5 lsb of rms noise or a noise limited snr of 69 db, indicating that noise alone does not limit the snr performance of the device (quanti- zation noise and linearity are also major contributors). this thermal noise may come from several sources. the drive source impedance should be kept low to minimize resistor ther- mal noise. some of the internal adc noise is generated in the wideband t/h. sampling adcs generally have input band- widths which exceed the nyquist frequency of one-half the sampling rate. (the AD9023 has an input bandwidth of over 100 mhz, even though the sampling rate is limited to 20 msps.) using the AD9023 layout information preserving the accuracy and dynamic performance of the AD9023 requires that designers pay special attention to the lay- out of the printed circuit board. analog paths should be kept as short as possible and be properly terminated to avoid reflections. the analog input connection should be kept away from digital signals paths; this reduces the amount of digital switching noise which is capacitively coupled into the analog section. digital signal paths should also be kept short, and run lengths should be matched to avoid propagation delay mismatch. the AD9023 digital outputs should be buff- ered or latched close to the device (< 2 cm). this prevents load transients which may feed back into the device. in high speed circuits, layout of the ground is critical. a single, low impedance ground plane on the component side of the board is recommended. power supplies should be capacitively coupled to the ground plane with high quality 0.1 m f chip ca- pacitors to reduce noise in the circuit. all power pins of the AD9023 should be bypassed individually. the compensation pin (comp pin 17) should be bypassed directly to the Cv s sup- ply (pin 15) as close to the part as possible using a 0.1 m f chip capacitor. multilayer boards allow designers to lay out signal traces with- out interrupting the ground plane, and provide low impedance ground planes. in systems with dedicated analog and digital grounds, all grounds for the AD9023 should be connected to the analog ground plane. in systems using multilayer boards, dedicated power planes are recommended to provide low impedance connections for device power. sockets limit dynamic performance and are not recom- mended for use with the AD9023. timing conversion by the AD9023 is initiated by the rising edge of the encode clock (pin 8). all required timing is generated inter- nal to the adc. care should be taken to ensure that the encode clock to the AD9023 is free from jitter that can degrade dy- namic performance.
C8C AD9023 rev. a pulse width of the adc encode clock must be controlled to en- sure the best possible performance. dynamic performance is guaranteed with a clock pulse high minimum of 25 ns. opera- tion with narrower pulses will degrade snr and dynamic per- formance. from a system perspective, this is generally not a problem because a simple inverter can be used to generate a suitable clock if the system clock is less than 25 ns wide. the AD9023 provides latched data outputs. data outputs are available two pipeline delays and one propagation delay after the rising edge of the encode clock (refer to the AD9023 timing diagram). the length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9023; these transients can detract from the converters dynamic performance. operation at encode rates less than 4 msps is not recommended. the internal track-and-hold satu- rates, causing erroneous conversions. this t/h saturation pre- cludes clocking the AD9023 in a burst mode. the duty cycle of the encode clock for the AD9023 is critical for obtaining rated performance of the adc. internal pulse widths within the track-and-hold are established by the encode com- mand pulse width; to ensure rated performance, minimum and maximum pulse width restrictions should be observed. opera- tion at 20 msps is optimized when the duty cycle is held at 55%. analog input the analog input (pin 12) voltage range is nominally 1.024 volts. the range is set with an internal voltage reference and cannot be adjusted by the user. the input resistance is 300 w and the analog bandwidth is 110 mhz, making the AD9023 useful in undersampling applications. the AD9023 should be driven from a low impedance source. the noise and distortion of the amplifier should be considered to preserve the dynamic range of the AD9023. encode ?.2v a in AD9023 12 8 17 w 62 w 0.1 m f 5 encode ?.2v ?.2v w (510 w on each data bit) w (510 w on each data bit) 10176 10176 figure 12. AD9023 evaluation board power supplies the power supplies of the AD9023 should be isolated from the supplies used for noisy devices (digital logic especially) to re- duce the amount of noise coupled into the adc. for optimum performance, linear supplies ensure that switching noise from the supplies does not introduce distortion products during the encoding process. if switching supplies must be used, decoupling recommendations above are critically important. the psrr of the AD9023 is a function of the ripple frequency present on the supplies. clearly, power supplies with the lowest possible fre- quency should be selected. printed in u.s.a. c1963C10C10/94 outline dimensions dimensions shown in inches and (mm). q-28 (ceramic dip) 0.225 (5.72) max 0.150 (3.81) min 0.015 (0.38) min 28 15 1 14 0.026 (0.660) 0.014 (0.356) 0.620 (15.75) 0.590 (14.99) 0.018 (0.457) 0.008 (0.203) 0.07 (1.78) 0.03 (0.76) 0.110 (2.79) 0.090 (2.29) 0.610 (15.49) 0.500 (12.70) 1.490 (37.85) max z-28 (ceramic leaded chip carrier) top view 0.050 (1.27) typ 1 14 28 15 0.025 (0.635) min 0.115 (2.921) max 0.765 (19.431) 0.745 (18.923) 0.060 (1.524) 0.040 (1.016) 0.165 (4.191) max 0.015 (0.381) min 0.51 (12.954) 0.49 (12.446) 0.73 (18.544) 0.71 (18.036) 0.012 (0.305) 0.009 (0.229)
|
